The continued scaling of semiconductor devices to ever smaller dimensions creates a number of manufacturing challenges. One process related to this trend involves the production of very thin wafers used in integrated circuit (IC) fabrication. Some current approaches in the semiconductor industry use “back-grinding” of integrated circuit wafers (also referred to as semiconductor wafers) to reduce their thickness. This practice involves the completion of the front or active side of a wafer, and the subsequent removal of excess substrate from the back side of the wafer.
After formation of the active circuits on the front side of a wafer, one of two processes take place. If the wafer is processed using a flip chip ball grid array (FCBGA) based method, the circuits are covered with laminating tape and the process continues with the back-grinding. If a carrier bond process for through silicon vias (TSV) is used, then a carrier wafer is bonded to the integrated circuit wafer with an adhesive before back-grinding excess substrate.
Using each of these methods is not without drawbacks, as defects can occur during the steps for protecting the active circuitry. For instance, if taping is used in an FCBGA process, then taping pressure and speed are a concern. If the pressure and/or speed are not correct, bubbling of tape can cause impurities to remain on the wafer. Improper taping can also lead to breakage of the wafer during the back-grinding process. Using a TSV method, improper pressures during application of the adhesive and carrier wafer can again lead to problems during back-grinding, such as wafer warpage and breakage.